Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device

ABSTRACT

A method to enhance the programmability of a prompt-shift device is provided, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. In one embodiment, no additional masks are employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer.

RELATED APPLICATION

This application is a continuation of U.S. Ser. No. 13/429,930, filedMar. 26, 2012, which is a divisional of U.S. Ser. No. 12/130,460, filedMay 30, 2008, now U.S. Pat. No. 8,278,197 the entire contents of eachare incorporated herein by reference. This application is also relatedto U.S. Ser. No. 13/430,018 filed Mar. 26, 2012.

FIELD OF THE INVENTION

The present invention relates to a nonvolatile memory cell. Moreparticularly, the present invention relates to a nonvolatile memory cellincluding at least one field effect transistor (FET) that has enhancedprogrammability. The invention also provides a method of fabricatingsuch a nonvolatile memory cell.

BACKGROUND OF THE INVENTION

In the semiconductor industry, it is oftentimes desirable to fabricate avery large-scale integrated (VLSI) circuit which includes a one-timeprogrammable (OTP) nonvolatile memory element that can be programmedeither during wafer probing or after packaging of the semiconductor die.For example, programming of an OTP nonvolatile memory element is used toprovide self-contained identification information about an individual ICdie or die revision. OTP nonvolatile memory can also be used forremapping addresses of defective DRAM (dynamic random access memory)cells so that functional redundant memory cells are addressed instead.OTP nonvolatile memory may also provide hard-coded digital trimming datafor precision analog elements.

There are several different methods known in the art to implementnonvolatile data storage on an IC die. In one method, metallic fuses canbe selectively programmed by exceeding a certain current and therebycreating an open circuit in the fuse. This changes the resistance of themetallic fuse from an initial low-resistance to a high-programmedresistance.

In another method, antifuses are selectively programmed by applying arelatively high-programming voltage to break down a dielectric materialcontacted by two conductive terminals of the antifuse. This permanentlychanges the resistance presented by the antifuse from a high initialresistance to a low-programmed resistance. The programmed resistanceobtained is typically on the order of several 1000 ohms.

In accessing the antifuse for a read operation, the programmedresistance is used, for example, to couple the input capacitance of alogic gate to a high logic level provided by a power supply, or,alternatively, to a low logic level provided by a connection to ground.The time required to charge or discharge the input capacitance of thelogic gate is proportional to the product of the programmed resistanceof the fuse and the input capacitance of the logic gate.

The required programming voltage of prior art fuses and antifuses toimplement OTP nonvolatile memory storage is quite high (on the order of10-12 volts) and oftentimes the high-programming voltages must be routedto other circuits in the IC which are not typically capable ofwithstanding such high voltages. Moreover, the introduction ofhigh-voltage programmable fuses and antifuses into an IC die may requiresome redesigns and process modifications in order to avoid damage to theIC die. In some instances, extra processing steps are needed whichincrease the overall production cost of the IC die. In addition torequiring high-programming voltages, prior art fuses and antifusesoccupy a large space on the IC die which detracts from the space wereother ICs devices can be formed.

In addition to the above, a nonvolatile memory cell can be formed usinga standard complementary metal oxide semiconductor (CMOS) field effecttransistor (FET) utilizing a mechanism in the device wherein electronsare injected into the dielectric spacer region that abuts the patternedgate stack. Omitting the halo/extension implants will cause the FET tobecome underlapped, which enhances the device. Using an underlapped FETas a ‘prompt-shift device’ is disclosed, for example, in U.S. Pat. No.6,518,614 to Breitwisch et al. and in a paper that was submitted at theMTDT 2005 conference entitled “A Novel CMOS Compatible EmbeddedNonvolatile Memory with Zero Mask Adder”.

Although the prompt-shift device disclosed in the above referencesprovides a means for programming a nonvolatile memory cell, the priorart prompt-shift devices require extremely long (on the order of about 1to about 5 seconds) programming times.

In view of the above, there is a need for providing a prompt-shiftdevice for use in a nonvolatile memory cell in which the programmingtime is less than 1 second.

SUMMARY OF THE INVENTION

The invention provides a method to enhance the programmability of aprompt-shift device, and thus reduce the programming time tosub-millisecond times.

The term “prompt-shift device” is used throughout the presentapplication to denote a FET including an underlapped diffusionstructure. By ‘underlapped diffusion structure’ it is meant a diffusionstructure (e.g., source/drain regions) in which no part thereof islocated directly beneath the gate. Instead, the underlapped diffusionstructure of the invention includes a portion that is located directlybeneath the source/drain dielectric spacer. The underlapped diffusionstructure induces hot electron injection into overlying dielectricspacers when the underlapped junction is biased as the drain. Electronsstored in the dielectric spacers modulate the source resistance of thememory cell when the underlapped junction is biased as the source in aread operation. Stored electrons are erased using hot hole injection.All the operations of the memory cell are performed with voltages nomore than 5, preferably less than 3.5, V that can be obtained from astandard input/output supply without charge pumping.

As stated above, the invention provides a method to enhance theprogrammability of a prompt-shift device and thus reduce the programmingtime to sub-millisecond times, by altering the extension and haloimplants (hereinafter halo/extension implants), instead of simplyomitting the same from one side of the device as is the case in theprior art prompt-shift devices mentioned above.

The invention uses an altered halo/extension implant to adjust (i.e.,tailor) the junction profile to enhance the electric field directlybeneath the extension dielectric spacer. One key feature of the alteredimplant in the invention is the halo (p-type for an nFET and n-type fora pFET) strength and location. In particular, the applicants havedetermined that increasing the halo dose (in a range from about 1.5 to 3times greater the standard halo dose) enhances the electric field of thedevice during operation. Also, the applicants have determined thatmoving the halo implant after the extension dielectric spacer has beenformed shifts the peak electric field to a location that is directlyunder the extension dielectric spacer. The term “peak electric field”denotes the region in the channel during the programming condition wherethe electric field is the highest. It is at this peak electric fieldlocation that electrons will have a maximum probability of beingtransferred from the channel into the above lying region. In comparison,and in conventional CMOS technology, it is common to perform the nFETextension and halo implants without the presence of any spacer. The pFETextension and halo implants in conventional CMOS processing aretypically performed after the extension dielectric spacer has beenformed.

The present invention discloses two methods that can be used tofabricate a prompt-shift device in which the programmability thereof isless than 1 second, preferably within the sub-millisecond time range. Inone embodiment of the present invention, no additional masks are usedduring the fabrication of the inventive prompt-shift device. In thisembodiment of the invention, the altered halo/extension implant isperformed to all the devices present on the substrate, e.g., the memorydevices as well as the logic devices. Moreover, the no additional maskembodiment of the present invention provides a prompt-shift deviceincluding symmetric, yet altered halo/extension regions on both sides ofthe device. In another embodiment of the invention, an additional maskis used and is formed atop a portion of the memory device and the logicdevices during the altered halo/extension implant. This embodiment ofthe invention permits the formation of asymmetric, yet alteredhalo/extension implant regions into only the memory devicesindependently from the other devices.

In general terms, the method of the present invention comprises:

providing at least one field effect transistor within a memory area of asemiconductor substrate, said at least one field effect transistorincluding a patterned gate region and an extension dielectric spacerlocated on sidewalls of said patterned gate region;

performing an extension ion implant into at said semiconductor substrateand on at least one side of the patterned gate region, said extensionion implant uses an ion dosage that is less than about 5E14 atoms/cm²;

performing a halo ion implant into said semiconductor substrate and onat least one side of the patterned gate region, said halo ion implantuses an ion dosage of greater than about 1E13 atoms/cm²;

forming a source/drain dielectric spacer onto exposed surfaces of saidextension dielectric spacer; and

forming source and drain regions on both sides of said patterned gateregion using said source/drain dielectric spacers as an implant mask.

In one embodiment of the invention, a mask is formed prior to performingthe extension ion implant and said mask remains in the structure untilafter performing the halo ion implant. This embodiment of the presentinvention results in a prompt-shift device having asymmetric, yetaltered extension/halo implant regions.

In another embodiment of the invention, no additional mask is presentduring the extension and halo implants. In this embodiment, aprompt-shift device having symmetric, yet altered extension/halo implantregions is provided.

In yet another embodiment of the present invention, the halo ion implantincludes a first ion implant step, followed by a second ion implantstep. In this two-step halo implant, the first and second ions are ofthe same conductivity type, yet they are comprised of different dopantions.

In a further embodiment of the invention, the at least one field effecttransistor is an n-FET, the extension ion implant includes selecting anion from Group VA of the Periodic Table of Elements, and the haloimplant includes selecting an ion from Group IIIA of the Periodic Tableof Elements. In a highly preferred embodiment, the Group VA ion for theextension implant is As, and the Group IIIA ion for the halo implantincludes a combination of In as a first ion, and B as a second ion.

In another aspect of the present invention, a prompt-shift device isprovided that comprises:

a semiconductor substrate having at least one field effect transistorlocated within a memory area of said substrate, said at least one fieldeffect transistor including a patterned gate region, an extensiondielectric spacer abutting sidewalls of said patterned gate region, anda source/drain dielectric spacer abutting sidewalls of said extensiondielectric spacer;

an altered extension region located within said semiconductor substrateand on at least one side of said patterned gate region, said alteredextension region having an extension ion dopant concentration of lessthan about 1E20 atoms/cm³;

an altered halo region located within said semiconductor substrate andon at least one side of said patterned gate region, said alteredextension region having a halo ion dopant concentration of greater thanabout 5E18 atoms/cm³, said altered halo region is in direct contact withsaid altered extension region;

source and drain regions located within said semiconductor substrate andon both sides of said patterned gate region, said source and drainregions are underlapped so that a portion thereof is located beneath thesource/drain dielectric spacer, and

wherein said altered extension region and said altered halo regionprovide a peak electrical field beneath the extension dielectric spacer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1B are pictorial representation (through cross sectional views)depicting the prompt-shift devices of the present application; FIG. 1Aillustrates a prompt-shift device including an asymmetric, yet alteredhalo/extension region, while FIG. 1B illustrates a prompt-shift deviceincluding a symmetric, yet altered halo/extension region.

FIGS. 2A-2G are pictorial representations (through cross sectionalviews) depicting the basic processing steps employed in a firstembodiment of the present invention in which one additional mask isemployed during the fabrication of the inventive prompt-shift deviceshown in FIG. 1A.

FIGS. 3A-3B are pictorial representations (through cross sectionalviews) depicting the basic processing steps employed in a secondembodiment of the present invention in which no additional mask isemployed during the fabrication of the inventive prompt-shift deviceshown in FIG. 1B.

FIG. 4 is a plot of III vs. accumulated program time of the inventiveprompt-shift device (curve A), a prior art prompt-shift device (curve B)and a conventional nFET.

DETAILED DESCRIPTION OF THE INVENTION

The present invention, which provides a prompt-shift device havingenhanced programmability and a method of fabricating the same, will nowbe described in greater detail by referring to the following discussionand drawings that accompany the present application. It is noted thatthe drawings of the present application are provided for illustrativepurposes only, and as such, the drawings are not drawn to scale.

In the following description, numerous specific details are set forth,such as particular structures, components, materials, dimensions,processing steps and techniques, in order to provide a thoroughunderstanding of the present invention. However, it will be appreciatedby one of ordinary skill in the art that the invention may be practicedwithout these specific details. In other instances, well-knownstructures or processing steps have not been described in detail inorder to avoid obscuring the invention.

It will be understood that when an element as a layer, region orsubstrate is referred to as being “on” or “over” another element, it canbe directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “connected” or “coupled” to another element, it canbe directly connected or coupled to the other element or interveningelements may be present. In contrast, when an element is referred to asbeing “directly connected” or “directly coupled” to another element,there are no intervening elements present.

Reference is first made to FIGS. 1A and 1B which are pictorialrepresentations (through cross-sectional views) showing differentembodiments of the inventive prompt-shift device. The prompt-shiftdevice illustrated in FIG. 1A includes asymmetric, yet alteredhalo/extension regions, whereas the prompt-shift device illustrated inFIG. 1B includes symmetric, yet altered halo/extension regions.

Specifically, each prompt-shift device is an underlapped FET whichcomprises semiconductor substrate 10 having isolation regions 12 locatedin, or partially within, a surface of substrate 10. Each underlapped FETdevice shown in FIGS. 1A-1B also includes gate dielectric 14 present ona portion of substrate 10, gate conductor 16 present atop gatedielectric 14, an extension dielectric spacer 18 present on at least theexposed vertical sidewalls of the gate dielectric and gate conductor,and a source/drain dielectric spacer 19 present on the exposed walls ofthe extension dielectric spacer 18.

Source/drain (S/D) regions 20 are located in the surface of thesubstrate, and as shown, the S/D regions are not present beneath thegate conductor. A channel region 22 is located in the substrate beneaththe gate region (which is defined by the gate dielectric and the gateconductor). The inventive structure shown in FIG. 1A also includes analtered extension implant region 24 located within the semiconductorsubstrate 10 on one side of the device. Region 26 denotes an alteredhalo implant region which is formed one side of the device in thisembodiment of the invention. It is noted that the source/drain regions,the altered extension region and the altered halo region are located atthe footprint of at least one field effect transistor. In FIG. 1A,reference numeral 26′ denotes a non-altered halo implant region, whilereference numeral 24′ denotes a non-altered extension implant region.

The inventive structure shown in FIG. 1B also includes an alteredextension implant region 24 located within the semiconductor substrate10 on both sides of the device. Region 26 denotes the altered haloimplant region which is formed on both sides of the device in thepresent invention. It is noted that the source/drain regions, thealtered extension region and the altered halo region are located at thefootprint of at least one field effect transistor.

During programming of the prompt-shift device of the present inventionusing programming voltages of less than about 5 V, preferably about 3.5V or less, charge gets trapped outside of the channel region such as inthe extension dielectric spacer, not within the channel region as is thecase with prior art FETs in which extension implant regions are presentbeneath the gate region. In the present invention, the prompt-shiftdevice is programmed by hot-electron injection into regions of the FEToutside the channel region when relatively low-programmable voltages(less than about 5 V) are employed.

The programmable state of the inventive prompt-shift device can be readusing a sense amplifier or other like device which is capable of readingthe programmable state of the underlapped device. For clarity, the senseamp is not depicted in the drawings of the present invention.

Due to the presence of altered halo/extension implant regions which areformed using a tailored prompt-shift implant process (to be discussed ingreater detail below), the inventive prompt-shift device has enhancedprogrammability, in which the programming time is reduced below 1second, in particular the inventive prompt-shift device can beprogrammed in the sub-millisecond time range.

The inventive prompt-shift devices shown in FIGS. 1A-1B will have ashift in threshold voltage due to channel hot-electrons injected fromthe substrate into the extension dielectric spacer 18 (and some chargemay get trapped in gate dielectric 14) much more readily than prior artoverlapped and underlapped FETs; this shift in threshold voltage isreferred to herein as a “prompt-shift”. The present invention uses thisphenomenon to build a very dense memory array.

The programming mechanics of the inventive prompt-shift device includethe following: Pulse drain and gate voltage to 3.5 V, while groundingthe source and substrate to program a “0” state. “1” state isnon-programmed state. To read the state, apply 2.5 V to the gate, 50 mVto the drain, ground the source and the substrate and measure the draincurrent. Note that the foregoing represents one possible way to programthe inventive prompt-shift device, and that other ways may also beemployed in the present invention.

The structures shown in FIGS. 1A-1B are comprised of conventionalmaterials well known to those skilled in the art and the structure isfabricated using either the processing steps which are shown in FIGS.2A-2G for the structure shown in FIG. 1A or the processing steps shownin FIG. 3A-3B for the structure shown in FIG. 1B.

Reference is first made to the processing steps shown in FIGS. 2A-2G inwhich a conventional CMOS processing flow is shown with the introductionof an additional mask and an altered halo/extension implant that areused in forming asymmetric, yet altered halo/extension implant regions.The embodiment shown in FIGS. 2A-2G allows one to tailor the asymmetric,yet altered halo/extension implant regions independently from all otherdevices.

FIG. 2A shows an initial structure that is employed in fabricating theinventive prompt-shift device shown in FIG. 1A. Specifically, FIG. 2Acomprises a semiconductor substrate 10 which has isolation regions 12formed therein. The isolation regions electrically isolate various ICdevices from other types of IC devices present in the substrate.Specifically, in FIG. 2A, some of the isolation regions separate thememory area (labeled as 100) where the inventive prompt-shift device isto be formed from the logic areas where a typically logic FET is to beformed. The logic areas are located to the periphery of the memory areaillustrated in the drawings.

The semiconductor substrate 10 employed in the present inventioncomprises any conventional semiconducting material, including, but notlimited to Si, Ge, SiGe, GaAs, InAs, InP and all other III/Vsemiconducting compounds. Layered substrate comprising the same ordifferent semiconducting material, e.g., Si/SiGe, andsilicon-on-insulators (SOIs) are also contemplated herein. The substratemay be of the n or p-type depending on the desired device to befabricated.

In some embodiments of the present invention, the semiconductorsubstrate 10 may comprise a hybrid oriented substrate which containssurface regions that have different surface orientations. The differentsurface orientations can be used to enhance the carrier mobility of aparticular FET.

In other embodiments of the present invention, the semiconductorsubstrate 10 may be strained, unstrained or it may contain strained andunstrained regions and/or layers therein.

Isolation regions 12, which may be local oxidation of silicon isolation(LOCOS) regions or trench isolation regions, are formed in portions ofsemiconductor substrate 10 using conventional processes well known tothose skilled in the art. For example, LOCOS regions are formed using aconventional LOCOS process in which exposed portions of substrate 10that are not protected by a patterned nitride layer are thermallyoxidized. The patterned nitride layer is then removed using aconventional stripping process that is highly selective in removingnitride as compared to Si.

Trench isolation regions are formed by first providing a patternedhardmask on the surface of the substrate using conventional deposition,lithography and etching processes well known to those skilled in theart. A timed etching process is then employed which forms trenches of adesired depth into exposed surfaces of the substrate. The trenches maybe optionally lined with a liner material prior to filling of the trenchwith a trench dielectric material such as TEOS (tetraethylorthosilicate)or SiO₂. In some instances, the trench dielectric material may beplanarized after deposition and/or a conventional densification processmay be employed to increase the density of the trench dielectricmaterial. The hardmask used in defining the trenches may be removedanytime after the trenches have been formed in the substrate using aconventional stripping process that is highly selective in removing ahardmask material from the structure. It is noted that in the drawingsisolation regions 12 are depicted as trench isolation regions.

Next, and as depicted in FIG. 2B, a patterned gate region including agate dielectric 14 and a gate conductor 16 is then formed on exposedportions of substrate 10 that do not include the isolation regions.Specifically, the gate dielectric 14 is formed on the surface ofsubstrate 10 using a conventional deposition process such as chemicalvapor deposition (CVD), plasma-assisted CVD, evaporation or chemicalsolution deposition. Alternatively, the gate dielectric 14 is formed bya conventional thermal growing process such as, for example, thermaloxidation. Gate dielectric 14 is composed of any dielectric materialincluding, but not limited to an oxide, a nitride, an oxynitride or anycombination thereof. The thickness of the gate dielectric 14 may varyand is not critical to the present application. Typically, the gatedielectric 14 has a thickness from about 2.0 to about 10.0 nm, with athickness from about 4.0 to about 6.0 nm being more highly preferred.Note that the thickness of the gate dielectric 14 used in forming theinventive prompt-shift device underlapped FET may be the same ordifferent than the other FET devices present in the structure.

The gate dielectric 14 may be patterned at this point of the inventiveprocess using conventional lithography and etching, or the gatedielectric 14 may be patterned at a later time, e.g., at the same timeas the gate conductor 16. The latter is preferred since it reduces thenumber of processing steps required in fabricating the gate region.

Gate conductor 16 is then formed atop the gate dielectric 14 using aconventional deposition process such as CVD, plasma-assisted CVD,evaporation, sputtering or chemical solution deposition. The gateconductor 16 is composed of any conductive material including, but notlimited to doped polysilicon or SiGe; a conductive elemental metal suchas W, Pt, Pd, Ru, Rh and Ir; alloys which include at least oneconductive elemental metal; silicides or nitrides of at least one of theabove-mentioned conductive elemental metals; or any combination thereof.When a combination of conductive materials is employed, an optionaldiffusion barrier material such as SiN, TaN, TaSiN, WN or TaSi₂ may beformed between each of the conductive materials. Note that a polysiliconor SiGe gate conductor may be formed using a conventional in-situ dopingdeposition process or, alternatively, the polysilicon or SiGe gateconductor may be formed by deposition and ion implantation.

The thickness of the gate conductor 16 may vary and is not critical tothe present invention. Typically, however, the gate conductor 16 has athickness from about 50 to about 250 nm, with a thickness from about 150to about 200 nm being more highly preferred. The gate conductor 16, andif not previous patterned, the gate dielectric 14, may be now patternedusing conventional lithography and etching. A dielectric cap, such as anitride cap, not shown, may be formed atop the gate conductor 16 priorto patterning the gate region using conventional processes well known tothose skilled in the art.

Next, and as shown in FIG. 2C, at least one extension dielectric spacer18 which is composed of a conventional dielectric such as an oxide,nitride, oxynitride or any combination thereof, is formed about eachpatterned gate region so as to protect at least the exposed sidewalls ofthe gate dielectric and gate conductor. In one embodiment, the extensiondielectric spacer 18 is comprised of a nitride. The extension dielectricspacer 18 is formed using conventional processes well known to thoseskilled in the art, including, for example, deposition and, optionally,etching. Prior to spacer formation, the exposed sidewalls of the gatedielectric and gate conductor may be subjected to a conventionalsidewall oxidation process which forms an oxide region (not shown) onthe exposed sidewalls. Note that the extension dielectric spacer 18 is athin spacer relative to the source/drain dielectric spacer to besubsequently formed.

Next, and as shown in FIG. 2D, a mask 29 is formed so as to block oneside of the structure, i.e., patterned gate region, while leavinganother side unprotected. Conventional extension implants and haloimplants are performed using conventional conditions well known in theart so as to form a non-altered extension implant region 24′ and anon-altered halo implant region 26′ on the side of the structure that isnot protected. The mask 29 and the additional mask 30 to be used in thenext step of the present invention comprise any conventional maskingmaterials including photoresists, hardmasks and multilayers thereof.Each mask 29, 30 is formed by deposition, lithography and etching andthe masks are removed after the implants utilizing conventional maskstripping processes well known to those skilled in the art. Thenon-altered extension implant region 24′ and the non-altered haloimplant region 26′ differ from the altered counterparts in at leastdoping concentration. The extension regions within the logic device canbe formed utilizing mask 29.

At this point of the invention, an additional mask 30, shown as shown inFIG. 2E, is at least formed over a portion of the patterned gate regionin the memory device area 100. The additional mask 30 may be formed overthe patterned gate region in the logic device area as well. Note thatone side of the patterned gate region in the memory device area 100 isexposed.

With the additional mask 30 in place, an altered extension implant andan altered halo implant (collectively referred to herein as an alteredhalo/extension implant) are employed. By “altered extension implant” itis meant that the extension implant is performed at a reduced dosage ascompared to a conventional extension implant (a conventional extensionimplant is performed using an ion dose that is about 5E14 atoms/cm² orgreater). The term “altered halo implant” denotes that the halo implantis performed at a higher dosage than a conventional halo implant (aconventional halo implant is performed using an ion dose that istypically about 1E13 atoms/cm² or less).

The altered halo/extension implant includes first performing anextension implant using a reduced ion implant dosage as compared to aconventional extension implant and then performing a first halo implantusing a higher ion implant dosage as compared to a conventional haloimplant. A second halo implant also using the higher ion implant dosagethan a conventional halo implant may optionally be performed. When thesecond halo implant is performed, the ion of the first halo implant isdifferent from the ion of second halo implant.

In particular, the altered extension implant is performed using ann-type ion (i.e., an ion such as P, As, and Sb from Group VA of thePeriodic Table of Elements) or a p-type ion (i.e., an ion such as B, Al,In from Group IIIA of the Periodic Table of Elements). The type ofdopant ion implanted will depend on the conductivity type of devicebeing fabricated. For example, an n-type extension implant is used informing an nFET, while a p-type extension implant is used for forming apFET. In a preferred embodiment of the invention, nFETs are formedwithin the memory area 100. In the preferred embodiment, the extensionimplant includes arsenic as the n-type dopant for the extension region,In as the ion for the first halo implant and B as the ion for theoptional second halo implant.

The altered extension implant is performed at an angle, as measuredrelative to the surface of the substrate, of from 0° to about 30°, withan angle from 5° to about 10° being more preferred. The alteredextension implant of the present invention is performed at an energyfrom about 5 to about 50 KeV, with an energy from about 10 to about 20KeV being more preferred for the altered extension implant. As statedabove, the altered extension implant is performed using an ion dosagethat is less than 5E14 atoms/cm² (i.e., the dosage of a conventionalextension implant). More preferably, the altered extension implant ofthe present invention is performed using an ion dosage from about 1E13to about 5E14 atoms/cm². In an even more preferred embodiment of theinvention, the altered extension implant is performed using an iondosage of about 1E14 atoms/cm².

Next, and with mask 30 also in place, the altered halo implant isperformed. As indicated above, the altered halo implant may include afirst halo implant using a first ion, and optionally a second haloimplant using a second ion that has the same conductivity, yet differsfrom the first ion. The type of ion used in the halo implant may varyand includes, an ion that is of a different conductivity type ascompared to the ion implanted into the altered extension region. In thepreferred embodiment, in which an nFET is formed, the first halo implantincludes an ion from Group IIIA such as, for example, B, Al, and In,with In being preferred. When the optional second halo implant isperformed in the preferred embodiment, the ion of the optional secondimplant is an ion from Group IIIA other than the ion used in the firsthalo implant. Preferably, and when the ion of the first halo implant isIn, the ion of the second halo implant is B.

The altered first halo implant is performed at an angle, as measuredrelative to the surface of the substrate, of from about 10° to about30°, with an angle from about 20° to about 30° being more preferred. Thealtered first halo implant of the present invention is performed at anenergy from about 50 to about 200 KeV, with an energy from about 110 toabout 140 KeV being more preferred for the altered first halo implant.As stated above, the altered first halo implant is performed using anion dosage that is greater than 1E13 atoms/cm² (i.e., the dosage of aconventional halo implant). More preferably, the altered first haloimplant of the present invention is performed using an ion dosage fromabout 3E13 to about 5E14 atoms/cm². In an even more preferred embodimentof the invention, the altered first halo implant is performed using anion dosage of about 6E13 atoms/cm².

When altered second halo implant is performed at an angle, as measuredrelative to the surface of the substrate, of from about 5° to about 30°,with an angle from about 5° to about 15° being more preferred. Thealtered second halo implant of the present invention is performed at anenergy from about 5 to about 50 KeV, with an energy from about 10 toabout 20 KeV being more preferred for the altered second halo implant.As stated above, the altered second halo implant is performed using anion dosage that is also greater than 1E13 atoms/cm² (i.e., the dosage ofa conventional halo implant). More preferably, the altered second haloimplant of the present invention is performed using an ion dosage fromabout 2E13 to about 5E14 atoms/cm². In an even more preferred embodimentof the invention, the altered second halo implant is performed using anion dosage of about 4.2E13 atoms/cm².

At this point of the invention, an activation anneal step may beperformed to activate the implanted dopant ions. The activation annealstep may also be omitted and performed in a later time of the inventiveprocess, i.e., after formation of the source/drain regions. Theconditions of the activation anneal may vary and are well known to thoseskilled in the art. Typically, the activation anneal is performed at atemperature of about 800° C. or greater.

The structure after performing the above altered halo/extension implantis shown in FIG. 2F. In this drawing, reference numeral 24 denotes the‘altered’ extension region of the invention, and reference numeral 26denotes the ‘altered’ halo extension region. After formation of alteredregions 24 and 26, the additional mask 30 is removed from the structureutilizing a conventional stripping process well known to those skilledin the art.

The altered extension region 24 that is formed using the alteredextension implant has an extension dopant ion concentration of less thanabout 1E20 atoms/cm³, with an extension dopant ion concentration fromabout 1E19 to about 8E19 being more preferred. The altered halo region26 that is formed has a halo dopant ion concentration of greater thanabout 5E18 atoms/cm³, with a halo ion concentration from about 8E18 toabout 5E19 being more preferred.

Next, and as shown in FIG. 2G, a source/drain dielectric spacer 19 whichmay be composed of the same or different insulator material as theextension dielectric spacer 18 is formed on the exposed sidewalls of theextension dielectric spacer 18 by deposition and etching. In a preferredembodiment of the invention, and when the extension dielectric spacer 18comprises a nitride, the source/drain dielectric spacer 19 comprises anitride/oxide stack. Note that source/drain dielectric spacer 19 isthicker than the extension dielectric spacer 18.

Next, source/drain diffusion regions (herein after source/drain regions)20 are formed in substrate 10 about each patterned gate region, e.g., atthe footprint of each patterned gate region. The source/drain regionsare formed using a conventional ion implantation process followed by anactivation annealing process that is performed at a temperature of about800° C. or higher. The resultant structure after forming thesource/drain regions 20 is shown in FIG. 1A. Note that in this figurethe source/drain regions are not present beneath the gate region in thememory region. Hence, the illustrated FET device of FIG. 1A is anunderlapped device that can be employed as an OTP element.

Because the inventive FET is greatly underlapped, increased hot-electroninjection into other regions of the FET beside the channel occurs. Inone embodiment, the increased hot-electron injection occurs into thespacers, particularly the extension dielectric spacer 18, that abut thegate region. The increased hot-electron injection results in a FETdevice that has a 50% or greater, preferably 100%, increase in thesource-to-drain resistance as compared to FETs that contain overlappedsource/drain regions.

Also, since an altered halo/extension implant has been performed, thepeak electric field is shifted from under the gate dielectric 14 tounder the extension dielectric spacer 18 and, as such, the inventiveprompt-shift device can be programmed much more quickly as compared toconventional FETs or prompt shift devices fabricated in U.S. Pat. No.6,518,614.

Reference is now made to FIGS. 3A-3B which illustrate the sequence ofprocessing used in forming the structure shown in FIG. 1B, i.e., theprompt-shift device including symmetric, yet altered extension and haloregions. In this embodiment of the present invention, the structureshown in FIG. 2C is first provided using the processing sequencedescribed above. Unlike the first embodiment, no additional mask 30 isapplied to the structure shown in FIG. 2C. The structure including noadditional mask 30 is then subjected to the altered extension implantand the altered halo implant mentioned above. FIG. 3A illustrates thestructure after the altered extension implant has been performed, whileFIG. 3B illustrates the structure after the altered halo implant hasbeen performed. After performing the altered halo/extension implant, thesource/drain dielectric spacer 19 and the source/drain regions 30 areformed as described above. Since no additional mask is employed in thisembodiment, a prompt-shift device including a symmetric, yet alteredhalo/extension region is provided.

The resultant structure after forming the source/drain regions 20 isshown in FIG. 1B. Note that in this figure the source/drain regions arenot present beneath the gate region in the memory region. Hence, theillustrated FET device of FIG. 1B is an underlapped device that can beemployed as an OTP element.

Because the inventive FET is greatly underlapped, increased hot-electroninjection into other regions of the FET beside the channel occurs. Inone embodiment, the increased hot-electron injection occurs into thespacers, particularly the extension dielectric spacer 18, that abut thegate region. The increased hot-electron injection results in a FETdevice that has a 50% or greater, preferably 100%, increase in thesource-to-drain resistance as compared to FETs that contain overlappedsource/drain regions.

Also, since an altered halo/extension implant has been performed, thepeak electric field is shifted from under the gate dielectric 14 tounder the extension dielectric spacer 18 and, as such, the inventiveprompt-shift device can be programmed much more quickly as compared toconventional FETs or prompt shift devices fabricated in U.S. Pat. No.6,518,614.

Reference is now made to FIG. 4 which is a plot of I_(o)/I vs.accumulated program time of the inventive prompt-shift device (curve A),a prior art prompt-shift device (curve B) and a conventional nFET. It isobserved that I_(o)/I (which is plotted on the y-axis) represents theprogrammability of the device. That is, I_(o)/I equal theI_non-programmed/I_programmed. As shown the inventive prompt-shiftdevice has a greater enhanced programmability as compared to the priorart devices shown in FIG. 4. The inventive prompt-shift deviceillustrated as curve A includes an asymmetric, yet alteredhalo/extension implant region in which the following conditions wereused: Arsenic extension implant dose 1E14 atoms/cm², a B first haloimplant dose 1.05E13 atoms/cm², and an In second halo implant dose(1.5E13 atoms/cm²). The prior art prompt-shift device represented bycurve B was made utilizing the basic process disclosed in U.S. Pat. No.6,518,614. The nFET represented by curve C is a conventional overlappeddevice.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the spirit and scope of the appendedclaims.

What is claimed is:
 1. A method of fabricating a prompt-shiftsemiconductor device comprising: providing at least one field effecttransistor within a memory area of a semiconductor substrate, said atleast one field effect transistor including a patterned gate region andan extension dielectric spacer located on sidewalls of said patternedgate region; performing an extension ion implant without a mask intosaid semiconductor substrate and on both sides of the patterned gateregion, said extension ion implant uses an ion dosage that is less thanabout 5E14 atoms/cm²; performing a halo ion implant without a mask intosaid semiconductor substrate and on both sides of the patterned gateregion, said halo ion implant uses an ion dosage of greater than about1E13 atoms/cm²; forming a source/drain dielectric spacer onto exposedsurfaces of said extension dielectric spacer; and forming source anddrain regions on both sides of said patterned gate region using saidsource/drain dielectric spacers as an implant mask.
 2. The method ofclaim 1 wherein said halo ion implant comprises a first halo ion implantstep using a first halo ion, and a second halo ion implant step using asecond halo ion.
 3. The method of claim 1 wherein said at least onefield effect transistor is an nFET, and said performing said extensionion implant includes selecting an extension dopant ion from Group VA ofthe Periodic Table of Elements and said performing said halo ion implantincludes selecting a halo dopant ion from Group IIIA of the PeriodicTable of Elements.
 4. The method of claim 1 wherein said performing saidextension ion implant includes using an energy from about 5 to about 5KeV and an implant angle of from 0° to about 30° as measured from asurface of said semiconductor substrate.
 5. The method of claim 1wherein said performing said halo ion implant includes implanting afirst halo ion using an energy from about 50 to about 200 KeV and animplant angle of from about 10° to about 30° as measured from a surfaceof said semiconductor substrate.
 6. The method of claim 5 wherein saidperforming said halo ion implant includes a second halo implant thatcomprises implanting a second halo ion using an energy from about 5 toabout 50 KeV and an implant angle of from about 10° to about 30° asmeasured from a surface of said semiconductor substrate.
 7. The methodof claim 1 wherein said extension ion implant forms an extension regionon both sides of the patterned gate region, each extension region has aterminal point that is located beneath said extension dielectric spacerand not aligned to an edge of said extension dielectric spacer or anedge of the patterned gate region.
 8. The method of claim 1 wherein saidhalo implant forms a halo implant region on both sides of the patternedgate region, each halo implant region has a terminal point locateddirectly beneath said extension dielectric spacer and not aligned to anedge of said extension dielectric spacer or an edge of the patternedgate region.
 9. The method of claim 1 wherein said source and drainregions have a terminal point that is located beneath said source/draindielectric spacer and not aligned to any edge of the source/draindielectric spacer.
 10. The method of claim 1 further comprising formingan oxide region by thermal oxide on exposed sidewalls of said patternedgate region prior to forming said extension dielectric spacer.
 11. Themethod of claim 3 wherein said extension dopant ion is arsenic and saidhalo ion implant includes In as said halo dopant ion.
 12. The method ofclaim 11 further comprising B as another halo dopant ion.
 13. The methodof claim 4 wherein said implant angle of said extension ion implant isfrom 5° to about 10°.
 14. The method of claim 4 wherein said energy ofsaid extension ion implant is from 10 KeV to 20 KeV.
 15. The method ofclaim 4 wherein said ion dosage of said extension ion implant is from1E13 atoms/cm² to less than about 5E14 atoms/cm².
 16. The method ofclaim 5 wherein said implant angle of said halo ion implant is from 20°to about 30°.
 17. The method of claim 5 wherein said energy of said haloion implant is from 110 KeV to 140 KeV.
 18. The method of claim 1wherein said ion dosage of said halo ion implant is from 3E13 atoms/cm²to less than about 5E14 atoms/cm².
 19. The method of claim 1 whereinsaid performing said extension ion implant forms an extension regionhaving an extension dopant concentration of less than about 1E20atoms/cm³.
 20. The method of claim 1 wherein said performing said haloion implant forms a halo implant region having a halo dopantconcentration of greater than about 5E18 atoms/cm³.